The flat panel display, such as liquid crystals display (LCD), with advantages of high quality, power saving, thin body and wide application field, has been widely used in many consuming electronic product, such as mobile phone, TV, personal digital assistant (PDA), digital camera, notebook, laptop, etc., and dominates the display field.
The active liquid crystals display comprises a plurality of pixels, and each pixel includes a thin film transistor (TFT). The gate of the TFT is connected to the horizontal scan line. The source of the TFT is connected to the vertical data line. The drain of the TFT is connected to the pixel electrode. A sufficient voltage is applied to the scan line to switch on all the TFTs connected to the scan line. At this time, the pixel electrodes on the horizontal scan line are connected to the vertical data lines, thereby to write the display signals on the data line into the pixel electrodes and to control the transmittances of different liquid crystals for achieving the effect of controlling colors and brightness. The driving of horizontal scan lines of the current active liquid crystals displays is fulfilled by external connected IC chips mainly. The external IC chips can control each stage of scan lines to charge and discharge stage by stage. The gate driver on array (GOA) technology utilizes the current process of fabricating array on the thin film transistor liquid crystals display panel to manufacture the driving circuit of gate lines on the array substrate, for realizing the driving method of scanning the gate lines row by row.
The current mainstream TFT-LCD display market includes three types, a twisted nematic (TN) or super twisted nematic (STN) type, an in-plane switching (IPS) type, and a vertical alignment (VA) type, wherein the VA type LCD shows a higher contrast compared to the other types, and is widely applied to large-size display, such as TV. The High Vertical Alignment (HVA) mode is one important branch in the VA modes. When the HVA liquid crystals display panel functions, the twist of the liquid crystals molecules in the liquid crystals layer is controlled by the vertical electric field formed between the pixel electrode of the array substrate and the common electrode of the color filter substrate. LC photo-alignment technology refers to exposing a LCD panel to ultraviolet when a voltage is being applied to the LCD panel, to cause the monomer of the LCD to react and allow a liquid crystals molecule to form a pre-tilt angle.
In the manufacturing process of LCD, it is necessary to test the products in some specific stages for finding problems, thereby to repair the products and promote the product yield. If it is required to test products, the GOA circuits and the active areas (AA) should be powered on. Therefore, it is necessary to dispose signal pads around peripheral wires for providing power via pins. In current GOA products, there are increasing demands such as high resolution, larger size and high frequency. For achieving these demands, it is necessary to provide extra signals for sharing the RC loading in product design, to make the main board have enough power for keeping signals stable. For example, in the GOA products, four clock signals required for high definition are added to be twelve clock signals required for the trigate of ultra-definition. Therefore, it is required for each set of pins of the testing device to add eight pins for performing tests. A photomask includes the patterns of multiple chips, so it is required to perform the test for multiple chips or the alignment process to liquid crystals simultaneously while considering production capacity. That is, the number of pads in current design needs to be added. Therefore, it is necessary to add 8×N pins in the testing device, wherein N is the number of chips on a substrate, and the cost would be increasing too much. In the meantime, too many pins also cause the tense space issue in design typography.
As shown in FIG. 1A, the design scheme of current normal HAV pads is illustrated. Multiple sets of high vertical alignment (HVA) pads 1 and others such as array test pads 2 and cell test pads 3 are disposed around peripheral wires of chips 4.
As shown in FIG. 1B, the specific types of pads included in the current HAV pads are illustrated. Each set of HAV pads 1 is applied to perform the test or alignment process to liquid crystals molecules. According to the specific GOA circuit structures on chips 4, a set of HAV pads 1 includes n clock pads CK1 . . . CKn for inputting clock signals, a color filter substrate common voltage pad CFcom for inputting a color filter substrate common voltage, an array substrate common voltage pad Acorn for inputting an array substrate common voltage, a DC high voltage pad VGH for inputting a DC high voltage, etc., and each pad is connected to the corresponding position of the peripheral wires according to the type thereof. The specific types and numbers of pads of each set of HAV pads can be determined according to demands of tests or alignment processes of liquid crystals for chips 4.
According to the current normal design of HAV pads, each chip 4 is corresponding to one set of HAV pads 1. If one set of HAV pads 1 includes M pads, for n chips 4, it needs N×M pads in the normal condition, thereby to have the number of pads in one set of HAV pads 1 increase too much, which would cause the tense space issue in design typography and increasing cost. If one set of HAV pads 1 is applied to perform tests or alignment process to liquid crystals, and in case the wiring in one chip 4 is short road, it is possible to cause the tests for other chips 4 and the alignment to liquid crystals are failed.